Process for forming interconnections in a multilayer circuit board

ABSTRACT

Electronic interconnections are formed between a plurality of layers of multilayer board by first applying a removable and reuseable dielectric mask over the surface of a circuit pattern formed on an insulating layer. The mask includes a pattern of openings which define locations for forming interconnecting members between portions of said circuit pattern and a subsequently formed circuit pattern. After the openings have been filled, the removable mask is replaced by a permanent insulating layer. The process of applying the mask and filling the openings is repeated to produce a multilayer board having a plurality of layers.

This invention relates to a process for forming electricalinterconnections between circuits comprising a multilayer board and,more particularly, to a process using a removable mask in forming apattern of solid metal members for making electrical interconnectionsbetween such circuits.

One present method of forming electrical connections in a multilayerboard utilizes a photo-resist layer which is processed for exposing thesurface of a circuit board at locations where electricalinterconnections are desired. A conducting material is deposited ontothe exposed areas. Inasmuch as a photo-resist layer is ordinarily nothicker than one-thousandths of an inch and because interconnections ofbetween five and ten thousandths of an inch may be required, thephoto-resist process must be repeated several times until the desiredheight is achieved.

Another process for forming electrical interconnections is described inPatent No. 3,311,966 issued Apr. 4, 1967 having the title of "Method ofFabricating Multilayer Printed Wiring Boards." That process generallycomprises chemically etching holes in a dielectric material sandwichedbetween conducting layers which are subsequently etched to form acircuit pattern. The etched holes are filled with a conducting materialwhich interconnects both sides of the circuit board. Additionaldielectric layers are then placed over the initial combination and theprocess repeated until a multilayer board is formed.

Other processes such as the one described in Patent No. 3,077,511,utilize pre-formed solder material with insulating sheets andinterconnecting sheets for providing interconnections between circuitsof a multilayer board. However, the thickness of the board is increasedby the use of the additional sheets and the density may be reducedbecause of the plurality of conductors integrally formed with theinterconnecting sheet. The plurality of conductors are used regardlessof the number of interconnections between the layers.

Applicant's process overcomes many of the objections to the referencedprocesses by filling openings provided in an adherable and removabledielectric masking layer with a conducting metal. The mask is placed ona circuit board so that the openings mate with portions of the circuitto which interconnections are to be formed. The filled openings fromconductive members for connecting to other circuit layers subsequentlyformed.

Subsequent to forming the conductive members, the board is processed toform an insulating layer over the circuit board surface and around themembers, leaving only the top surfaces of the members exposed forconnection to subsequent layers.

Therefore, it is an object of this invention to provide a process forforming solid metal interconnections between circuits of a multilayerboard by use of a removable mask.

It is still another object of this invention to form conductinginterconnections for one circuit of the multilayer board to anothercircuit without the necessity for making a series of the depositions inorder to form the interconnecting members.

It is still a further object of this invention to provide a process forforming interconnections within a multilayer board by forming solidmembers to which circuits of a different layer are connected.

Still a further object of this invention is to provide a process forachieving high interconnection density by using a mask which defines apattern of multilayer interconnections.

A still further object of this invention is to provide for increasedflexibility and reliability in making interconnections between circuitsof a multilayer board.

These and other objects of this invention will become more apparent inconnection with the following drawings of which,

FIG. 1 is a block diagram representation of the process steps utilizedin forming multilayer interconnections.

FIGS. 2(a) through 2(j) represent one embodiment of a multilayer boardduring various phases of fabrication.

Referring now to FIG. 1 wherein is shown a general sequence of stepscomprising the process for forming interconnections between circuits.

In step 1 a circuit board comprised of a circuit pattern on one or bothsides of a dielectric layer is produced. In the usual embodiment, thecircuit is formed by etching a conducting material such as copper into adesired pattern of conductors and terminal areas. Electrical connectionsmay be between the circuit patterns on both sides of the board byelectro-plating openings through the dielectric with a conductingmaterial.

In step 1(a) a masking layer is prepared for covering areas of thecircuit pattern where interconnections to subsequently formed circuitpatterns are not desired. In other words, the mask comprises adielectric material such as epoxy glass which has a pattern of openingstherethrough for exposing the portion of the circuit pattern to whichinterconnections are to be affixed. The openings are filled with aconducting material such as copper in subsequent steps.

The sequence for producing the circuit board and the mask is notimportant. Either one may be formed before the other or both may beformed simultaneously.

In step number 2 the mask, which may have, for example, a pressuresensitive adhesive attached to the side thereof adjacent to the circuitpattern, is mated with the pattern so that the mask openings correspondwith areas of the circuit pattern which are to be interconnected toother patterns.

Means may be provided for filling the plurality of openingssimultaneously with the conducting material. For example, if an electrodeposition process is used, the entire surface is coated with a thinconducting layer such as copper which functions as an electrode for allthe mask openings. The layer is deposited on the surface prior toaffixing the mask and in a specific embodiment is continuous over thecircuit board surfaces.

In other embodiments the circuit may be masked so that the layercontacts the edge of the circuit but does not cover it. The conductinglayer could also be formed so that it covers or contacts only theportions of the pattern to which depositions are to be made. If thelayer is omitted from the top surface of the pattern, a relativelyimproved bond between the pattern and subsequent depositions may result.

When the mask is placed on the board, the openings are filled to the topsurface of the mask with the conducting material. Afterwards, the maskand the continuity layer are removed, leaving only the circuit patternand the protruding interconnections.

In step number 3, an insulation layer similar to the mask, is fabricatedhaving a pattern of openings which mate with the interconnections formedin step number 2. It has a thickness compatible with the height of theinterconnecting members so that the top surface of the layer and thetops of the protrusions are in the same plane. The insulating layer maybe fabricated at the same time as the mask, and is laminated to thecircuit board following its disposition thereon.

In other embodiments, in lieu of forming the insulating layer, aninsulating material such as uncured epoxy resin could be spread over thesurface of the circuit board until the material is flush with the topsurfaces of the interconnections.

Subsequently, the cycle is repeated until as many layers as are neededto complete the multilayer board are fabricated.

Referring now to FIG. 2(a), wherein is shown a cross-sectional view oflayer 21 having a pattern of openings 22 produced through the layer. Ina preferred embodiment, the layer is comprised of a dielectric materialsuch as an epoxy glass resin. A conducting layer 20 such as copper isshown as bonded to one surface of layer 21. In other embodiments, aconducting layer could be provided for both surfaces. In eitherembodiment, after the openings are filled and a circuit pattern producedon both sides of the board, both sides of the board may be processedsimultaneously.

Various methods may be used to produce the pattern of openings in layer21. For example, an epoxy glass layer ranging in thickness from 0.004 to0.015 inch may be either mechanically or chemically drilled.

One etchant suitable for etching a conducting layer of copper is FeCl₃and an etchant for drilling the epoxy glass is a solution comprising HFand H₂ SO₄.

After the openings are formed through layer 21, a conducting material23, such as copper, is provided in the openings as shown in FIG. 2(b).The conducting material is made level with the top surface of thedielectric by, for example, depositing copper therein from anelectro-plating copper bath.

In another example, the openings may be filled by forcing a liquidgallium alloy therein and subsequently hardening the material.

In FIG. 2(c) the surface of the dielectric is coated with a conductinglayer such as copper or nickel, having an approximate thickness of onethousandths of an inch. In one embodiment, the surface is firstelectroless copper plate to form layer 25 and then electro-plated withcopper to form layer 26.

If the copper does not readily adhere to the dielectric, the surface maybe coated with adhesive layer 24 to insure good contact between thecopper layer and the board surface. An adhesive such as B-staged epoxymay be used for that purpose. In other processes, sensitizers known tothose skilled in the art may be used.

In the next step, shown in FIG. 2(d) both surfaces (20 and 26 of FIG.2(c)) are coated with a photosensitive material and exposed toultraviolet radiation to form circuit patterns on both sides of theboard. The unexposed portions of the material are washed away leavingthe copper layer covered by the exposed portions. The copper materialnot covered is etched away to form circuit patterns 27 and 27' on theboard's surfaces. The two patterns are interconnected through theconducting material filling openings 22. After the etching is completed,the remaining photo-sensitive material is removed from the top of thecircuit pattern. The adhesive may also be removed at that time.

In lieu of using a deposition process, followed by an etching process, acircuit pattern could be printed on by using silk screen method or othermethods known in the art.

Conducting means may be disposed on the surface of the board forproviding an electrode connection to at least the portions of thecircuit pattern to which interconnections are to be made. For example, athin layer of copper may be flash plated on the surfaces followed by anelectro-plated copper deposit for approximately one minute to providethe electrical continuity necessary to complete the process. The boardis shown with continuity layers 32 and 32' in FIG. 2(e).

Electrical continuity may be important because as shown in FIGS. 2(f)and 2(g) the interconnecting members can be formed simultaneously bymaking a single electrode connection to the layer. An electrodeconnection could be provided for each opening, however. In addition, aconducting sheet or plate with openings matching the circuit pattern maybe disposed over the surface as an electrode.

Masks 28 and 28' have pressure sensitive adhesive layers 29 and 29'coated on the surfaces thereof adjacent to the circuit board surfaces.The mask is pressed against the board surface.

The mask may be produced in the same manner as described for layer 21.In certain embodiments, layer 21 may be identical to mask 28 except forthe addition of the pressure sensitive adhesive layer 29. The adhesivemay be sprayed onto the surface to a thickness of approximately .001inch. It is desirable to limit the thickness to no more than isnecessary to effect good adhesion between the mask and the boardsurface. Excessive amounts may be squeezed into the mask openings. Inapplying the adhesive, precaution must be taken to prevent the adhesivefrom entering the openings. In one embodiment air is directed throughthe openings during application of the adhesive to keep the openings 30and 30' cleared of the adhesive.

After the masks are properly placed on a circuit board and an electricalconnection is made to each continuity layer, the assembly is immersed inan electro-plating copper bath until the openings are filled with copperto form members 33 and 33' as shown in FIG. 2(g).

The masks are then removed as shown in FIG. 2(h) and the board surfacescleaned with a solvent to remove the remaining adhesive.

Subsequently, the assembly is flash etched in a ferric chloride bath forapproximately 15 to 20 seconds to remove the continuity layer from theareas of the circuit not comprising part of the circuit pattern. Inother words, the layer is relatively thin so that the etchant removesthe copper down to the dielectric material without etching awaysubstantial portions of the copper comprising the circuit pattern andthe electrical interconnections previously formed.

The board comprises circuit patterns with producing members 33 and 33'for interconnecting with other patterns to be formed as part of themultilayer board. The board, after the etching is finished, is shown inFIG. 2(i).

In certain embodiments one or more of the members may not be connectedto a subsequent layer but instead may be increased in height by asubsequent deposit to interconnect with a circuitry of another layer.This added feature reduces certain of the registration problems of theprior art and provides increase strength and reliability to thecompleted board.

Also, although four interconnecting members are shown, it should beobvious that more than the four or a plurality of patterns, could befabricated by the process described herein.

Insulating layers 34 and 34' (shown in FIG. 2(j)), having a pattern ofopenings identical to the pattern of members, are coated with laminatingadhesives 35 and 35' such as an epoxy adhesive and placed into positionon the board. In the alternative, the adhesive could be sprayed directlyonto the surface of the board and the insulating layers placed onto theapplied adhesive. After the insulating layers are in place, thecombination is pressed together and heated until it is cured.

The insulating layer may be formed at any time prior to its use,although in a preferred embodiment, it is formed at the time the maskand the dielectric layers are formed and in the same manner. In oneembodiment, the removable masks may be cleaned and used as theinsulating layers.

The completed board showing the insulated layers and the top surfaces ofthe interconnection members is shown in FIG. 2(j).

In another embodiment, the insulating layers could be applied byspraying on an uncured epoxy until the material is flush with the topsurfaces of the interconnecting members. After application of the epoxy,it is cured.

If additional layers are required the process as described beginningwith FIG. 2(a) is repeated until as many layers as are desired have beenfabricated.

Although the invention has been described and illustrated in detail, itis to be understood that the same is by way of illustration and exampleonly, and is not to be taken by way of limitation; the spirit and scopeof this invention being limited only by the terms of the appendedclaims.

We claim:
 1. A process for forming electrical connections between circuit layers of a multilayer board, said process comprising the steps of,producing a circuit pattern on at least one surface of an insulating substrate, covering said circuit pattern and said one surface with a thin conducting layer, disposing a reusable mask over said thin conducting layer, said mask having a pattern of openings defining locations for electrical connections to said circuit pattern, filling said openings with a conducting material to form conducting members on said circuit pattern, removing said reusable mask and the portion of said thin conducting layer on said one surface, applying an insulating layer over the surface of said insulating substrate and around said conducting members, the surface of said insulating layer and the tops of said conducting members being in approximately the same plane, producing a second circuit pattern on the surface of said insulating layer, said circuit pattern having portions connected to at least certain of said conducting members.
 2. The process as recited in claim 1, including the steps of,covering said second circuit pattern and the surface of said insulating layer with a second thin conducting layer, disposing said reusable mask over the surface of said second thin conducting layer, said mask having a pattern of openings defining locations for electrical connections to said second conductor pattern, filling said openings with a conducting material to form second conducting members on said second circuit pattern, removing said reusable mask and the portions of said second thin conducting layer on said insulating layer, applying an insulating layer on the surface of said first recited insulating layer and around said second conducting members, the surface of said second recited insulating layer and the tops of said second conducting members being in approximately the same plane, forming a third circuit pattern on the surface of said second recited insulating layer, said circuit pattern having portions connected to at least certain of said second conducting members. .Iadd.
 3. A method of fabricating an individual layer of a multilayer printed circuit board, comprising the steps of: forming a printed circuit on an insulator substrate; coating said printed circuit with a thin conductive layer of material; conforming an apertured masking material to said conductive layer on said printed circuit on said insulator substrate; said masking material including apertures therein in the desired pattern of at least one interlayer connector; electroforming said connector using said conductive layer as an electrical path in the electroforming operation; removing the masking material and the resultant exposed material of the conductive layer; and insulating the printed circuit and the interlayer connector, leaving an exposed surface at the end of said interlayer connector. .Iaddend. 